{"id":64,"date":"2021-06-07T19:24:26","date_gmt":"2021-06-07T19:24:26","guid":{"rendered":"https:\/\/webspace.nyit.edu\/educationbase\/?page_id=64"},"modified":"2025-01-17T20:52:57","modified_gmt":"2025-01-17T20:52:57","slug":"page-3","status":"publish","type":"page","link":"https:\/\/pages.nyit.edu\/zli75\/page-3\/","title":{"rendered":"ASIC, DSP, FPGA programming"},"content":{"rendered":"
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\"\"<\/figure>\n<\/div>\n\n\n

CPU vs GPU vs FPGA vs ASIC
Flexibility < ——> Efficiency
<\/p>\n\n\n\n


1. DSP: digital signal processors (TI, Freescale\/NXP, ADI)<\/strong>
GitHub – mikeroyal\/DSP-Guide: Digital Signal Processing(DSP) Guide<\/a>
Introduction \u2014 PySDR: A Guide to SDR and DSP using Python<\/a>
B4860-Baseband-Processor<\/a><\/p>\n\n\n\n

<\/p>\n\n\n\n

<\/p>\n\n\n\n

2. ModelSim RTL (VHDL, Verilog)<\/strong>
Reference source code: VHDL coding tips and tricks (<\/a>vhdlguru.blogspot.com<\/a><\/strong>)<\/a>
Download: www.intel.com \u203a content \u203a wwwModelSim-Intel\u00ae<\/a><\/strong>

Running VHDL Simulation with ModelSim<\/strong>
write your VHDL_code.vhd
write the test_bench.vhd
compile –> simulation<\/em><\/p>\n\n\n\n

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3. Programming Language C+<\/strong>+ : cplusplus.com\/doc\/tutorial\/<\/a>

C\/C++ tool installation, edit, compile and run<\/strong>

1) Download the MS Visual Studio<\/strong> from: https:\/\/visualstudio.microsoft.com\/downloads\/<\/a>
Or, Download MS Visual Studio from: https:\/\/visualstudio.microsoft.com\/vs\/older-downloads<\/a>
(Download Visual Studio Tools – Install Free for Windows, Mac, Linux (microsoft.com)<\/a> )

2) Or, Download the Code Blocks<\/strong> from: https:\/\/www.codeblocks.org<\/a><\/p>\n\n\n\n

3) Learning C\/C++<\/strong> in Visual Studio: https:\/\/learn.microsoft.com\/en-us\/cpp\/overview\/visual-cpp-in-visual-studio?view=msvc-170<\/a>

Coding example: The Factor-Weighted-Rating<\/strong> Model by C++<\/p>\n\n\n\n

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<\/p>\n\n\n\n

<\/p>\n\n\n\n

4. SystemC<\/strong><\/strong>: System Level Design and Verification <\/strong>
systemC.org<\/a>
http:\/\/www.ocpip.org<\/a>
Learn SystemC\u00a0 – Introduction<\/a><\/a><\/p>\n\n\n\n

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<\/p>\n\n\n\n


5. ASIC and FPGA design, simulation and verification Suites<\/strong><\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

1). Vivado<\/strong> and Quartus<\/strong> are specialized for FPGA workflows, tightly coupled with their respective hardware.
2). Cadence<\/strong> and Synopsys<\/strong> dominate ASIC\/SoC design but offer limited FPGA workflows, with Synopsys’ HAPS<\/strong> and Siemens’ Veloce<\/strong> filling the FPGA-based emulation niche.
3). Siemens (Mentor Graphics)<\/strong> uniquely bridges both ASIC and FPGA workflows, providing tools for synthesis, debugging, and emulation.
<\/p>\n\n\n\n



<\/p>\n","protected":false},"excerpt":{"rendered":"

CPU vs GPU vs FPGA vs ASIC Flexibility < ——> Efficiency 1. DSP: digital signal processors (TI, Freescale\/NXP, ADI)GitHub – mikeroyal\/DSP-Guide: Digital Signal Processing(DSP) GuideIntroduction \u2014 PySDR: A Guide to SDR and DSP using PythonB4860-Baseband-Processor ...<\/p>\n","protected":false},"author":163,"featured_media":0,"parent":0,"menu_order":5,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-64","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/pages\/64","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/users\/163"}],"replies":[{"embeddable":true,"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/comments?post=64"}],"version-history":[{"count":0,"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/pages\/64\/revisions"}],"wp:attachment":[{"href":"https:\/\/pages.nyit.edu\/zli75\/wp-json\/wp\/v2\/media?parent=64"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}